1. Field of the Invention
The present invention relates generally to frequency synthesizers and more specifically to circuitry for producing a phase-locked clock pulse stream of desired frequency using all digital circuit components and circuitry for utilizing the phase-locked pulse stream for producing a frequency modulated signal.
2. Description of the Related Art
FIGS. 3, 4 and 5 are illustrations of typical examples of phase locked loops generally used in prior art frequency synthesizers. In FIG. 3 the phase locked loop is comprised by a voltage controlled oscillator 1 (or voltage controlled crystal oscillator), a phase detector 2 for making a phase comparison between a reference frequency (Fref) and the output of the voltage controlled oscillator and a low-pass filter 3 for smoothing the output of the phase detector 2 to produce a d.c. frequency control signal which drives the voltage controlled oscillator 1 to produce an output signal of desired frequency (Fout). In FIG. 4, a given frequency is synchronized to a reference frequency by coupling the output of the voltage controlled oscillator 1 to a divide-by-N counter 4. Using a second divide-by-M counter 5 the reference frequency is divided by M so that the reference frequency is reduced to a level comparable at the inputs of the phase detector 2 to the output of the divide-by-N counter 4.
If the output of the voltage controlled oscillator 1 is equal to (N/M)xc3x97Fref (reference frequency), the frequency synthesizer can produce an output frequency with the same level of stability as the reference frequency. In addition, the phase locked loop of this type is used in most cases to produce a signal which serves to determine the transmit frequency of a wireless system at a desired frequency on an as-needed basis. When a need exists for changing the output frequency, the integer N is controlled according to the desired frequency. However, in terms of the loop stability and the time taken to change frequencies, the phase locked loop of FIG. 4 is not satisfactory. In order to solve this problem, a direct digital synthesizer has been developed as shown in FIG. 5. In the DDS phase locked loop, the reference frequency is controlled to produce a desired output frequency. A high stability oscillator is connected to a read only memory 6 in which various waveforms are stored in different address locations. By switching between different address locations, reference frequencies are altered. Since the speed at which the reference frequency is changed depends on the speed at which the address locations are switched, it is possible to perform high speed switching of reference frequency. By using the generated signal as a reference frequency of a phase locked loop, the output signal of the voltage controlled oscillator 1 is switched at a high speed. Since the operation of the phase locked loop of this type is irrelevant to the basic parameters of the phase locked loop, i.e., the sensitivity of the voltage controlled oscillator, the sensitivity of the phase detector and the filter coefficient, very high loop stability can be obtained.
However, the prior art phase locked loops require the use of analog circuit components such as voltage controlled oscillator and lowpass filter. In addition, while satisfactory for operation at relatively high frequencies, the prior art suffers poor stability for operation at relatively low frequencies. The poor stability can only be solved by the use of a large capacitor and a large resistor for the lowpass filter.
It is therefore an object of the present invention to provide a full digital phase locked loop that produce a stabilized output frequency without using analog circuit components.
According to a first aspect of the present invention, there is provided a full digital phase locked loop comprising a first counter for continuously counting pulses of a first clock pulse stream and producing a varying count number of the counted pulses, a second counter for counting pulses of a second clock pulse stream and producing a reference signal when a predetermined number of the pulses is counted, summation circuitry having a plurality of augend input terminals for receiving the varying count number from the first counter, a plurality of addend input terminals and a plurality of output terminals, one of the output terminals producing a comparison signal, an exclusive-OR gate for detecting an interval between the comparison signal and the reference signal, resettable counter circuitry for counting pulses of the second pulse stream during the detected interval and producing a count number of the counted pulses and resetting the count number at periodic intervals, and differentiation circuitry for differentiating count numbers from the resettable counter circuitry and producing a differentiated count number and supplying the differentiated count number to the plurality of addend input terminals of the summation circuitry.
According to a second aspect, the present invention provides a method of producing a desired frequency comprising the steps of (a) continuously counting pulses of a first clock pulse stream and producing a varying digital count number of the counted pulses, (b) counting pulses of a second clock pulse stream and producing a reference signal when a predetermined number of the pulses is counted, (c) summing the varying digital count number of step (a) with a digital difference signal to produce a comparison signal, (d) detecting an interval between the reference signal and the comparison signal, (e) counting pulses of the second pulse stream of step (b) during the detected interval and producing a digital count number of the counted pulses, (f) differentiating digital count numbers successively generated by step (e) to produce a differentiated digital count number, and (g) repeating steps (c) to (f) by using the differentiated digital count number of step (f) as the digital difference signal of step (c).
According to a third aspect, the present invention provides a frequency synthesizer comprising a first pulse generator for producing a first clock pulse stream, a first counter for continuously counting pulses of the first clock pulse stream and producing a varying count number of the counted pulses, a second pulse generator for producing a second clock pulse stream,a second counter for counting pulses of the second clock pulse stream and producing a reference signal when a predetermined number of the pulses is counted, summation circuitry having a plurality of augend input terminals for receiving the varying count number from the first counter, a plurality of addend input terminals and a plurality of output terminals, one of the output terminals producing a comparison signal, an exclusive-OR gate for detecting an interval between the comparison signal and the reference signal, resettable counter circuitry for counting pulses of the second pulse stream during the detected interval and producing a count number of the counted pulses and resetting the count number at periodic intervals, and differentiation circuitry for differentiating count numbers from the resettable counter circuitry and producing a differentiated count number and supplying the differentiated count number to the plurality of addend input terminals of the summation circuitry. With this arrangement, an output clock pulse stream of desired frequency can be obtained at one of the output terminals of the summation circuitry.
According to a fourth aspect, the present invention provides a frequency modulator comprising a first pulse generator for producing a first pulse stream, a first counter for continuously counting pulses of the first pulse stream and producing a varying count number of the counted pulses, a second pulse generator for producing a second pulse stream, a second counter for counting pulses of the second pulse stream and producing a reference signal when a predetermined number of the pulses is counted, first summation circuitry having a plurality of augend input terminals for receiving the varying count number from the first counter, a plurality of addend input terminals and a plurality of output terminals, one of the output terminals producing a comparison signal, an exclusive-OR gate for detecting an interval between the comparison signal and the reference signal, resettable counter circuitry for counting pulses of the second pulse stream during the detected interval and producing a count number of the counted pulses and resetting the count number at periodic intervals, differentiation circuitry for differentiating count numbers from the resettable counter circuitry and producing a differentiated count number and supplying the differentiated count number to the plurality of addend input terminals of the summation circuitry, and second summation circuitry for summing a digital modulating signal with the differentiated count number to produce a set of output signals indicating the summed differentiated count number and supplying the set of output signals to the addend terminals of the first summation circuitry. With this arrangement, a frequency modulated signal can be obtained at one of the summation output terminals of the first summation circuitry.